This invention relates in general to television receiver tuning systems and in particular to television receiver tuning systems incorporating programmable nonvolatile memories for storing television channel tuning information.
As discussed previously in the related Skerlos application, memories are generally classifiable into two groups--volatile and nonvolatile, the former "losing their memories" when power is removed. Memories are further classified into alterable and nonalterable, depending upon whether their contents may be changed after initial programming. In television tuning systems, many types of memories are used for storing channel tuning information.
Since nonvolatile memories effectively retain stored information indefinitely without the need for externally applied power, their advantages over memories which require periodic "refreshing" are obvious. While in a television receiver the requirement of periodic refreshing may be readily met by appropriate circuitry, difficulties arise when the possibilities of disconnecting the receiver from the power source, or a failure in the power source, are considered. In these instances a standby power supply, such as a battery, is required to prevent loss of system memory. This of course adds to receiver complexity and adds economic and reliability burdens.
If the system only requires fixed memories, simple "read only" types will suffice. These memories may even take the form of "hard-wired" arrays that require no external power or periodic refreshing. Unfortunately, the custom-alterable type memory is most often required in a television receiver, either to permit fine tuning or to compensate for changes in the frequency relationship between the transmitted signals and the programmed tuning system frequencies, whether due to component aging or specific signal conditions. Thus for television receivers, an alterable memory which does not require an external power source is highly desirable.
A particularly attractive memory which meets the criteria is the MNOS type (metal nitride oxide semiconductor). Such memories are fabricated in integrated circuit form and are characterized by a charge injection layer in which charge carriers may be moved about by application of appropriate potentials. The semiconductor charge carriers are literally forced into and out of the layer by the potentials and remain captive until electrically forced to move. A pattern of charge conditions is left which is used for memory purposes.
An unfortunate characteristic of memories of this type is that they "wear out" with use. Consequently, their active service life puts a limit on the useful life of any device incorporating them. Even so, the advantages of the no-standby-power-MNOS memory outweigh the disadvantages of memories which require periodic refreshing and standby power. It is therefore incumbent upon the tuning system designer desiring to use such memories to minimize their activation time to prolong their useful service lives in the receivers.
A television receiver incorporating a memory for storing channel tuning information generally includes means indicating when a change in channel selection has been or is desired to be made. A "channel change" signal should indicate that new channel address information has been put into the system or that some other indication, such as a channel UP/DOWN signal has been received. Prior art systems are generally of two types, the first including separate means developing an independent signal when the channel change is initiated and the second including means scanning the channel address inputs to determine when a channel address change has been initiated. While both add components and circuit complexity, in the latter the memory is continually re-addressed which, in the case of an MNOS type memory, uses up its life.
With the circuit of the copending Skerlos application, channel address input information is stored in a register as well as used to address the memory. A comparison circuit is supplied with the channel address information at one set of input terminals. The stored information is "clocked in" to create a first delay between the two informations at the comparison circuit inputs for sensing that a change in channel address input has occurred. The comparison circuit output is coupled to pulse means which enables reading of the memory contents only in response to an appropriate signal indicating a difference between the comparison circuit inputs.
The circuit of the present invention assures a second minimum delay between the channel address change and activation of the memory to enable the new memory location to be addressed prior to its activation.